@@ -15,48 +15,48 @@ enum {
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CLD, CLI, CLV, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY, JMP,
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JSR, LDA, LDX, LDY, LSR, NOP, ORA, PHA, PHP, PLA, PLP, ROL, ROR, RTI,
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RTS, SBC, SEC, SED, SEI, STA, STX, STY, TAX, TAY, TSX, TXA, TXS, TYA,
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- SLO, AXS, LAX,
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+ SLO, AXS, LAX, SAX,
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XXX,
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};
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enum { IMP, IMM, ABS, ABSX, ABSY, ZP, ZPX, ZPY, IND, INDX, INDY, ACC, REL};
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const int OPCODE_TABLE[256 ] = {
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- BRK, ORA, XXX, XXX, XXX, ORA, ASL, XXX, PHP, ORA, ASL, XXX, XXX, ORA, ASL, XXX ,
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- BPL, ORA, XXX, XXX, XXX, ORA, ASL, XXX, CLC, ORA, XXX, XXX, XXX, ORA, ASL, XXX ,
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+ BRK, ORA, XXX, XXX, XXX, ORA, ASL, XXX, PHP, ORA, ASL, XXX, XXX, ORA, ASL, SLO ,
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+ BPL, ORA, XXX, XXX, XXX, ORA, ASL, XXX, CLC, ORA, XXX, XXX, XXX, ORA, ASL, SLO ,
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JSR, AND, SLO, XXX, BIT, AND, ROL, XXX, PLP, AND, ROL, XXX, BIT, AND, ROL, XXX,
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BMI, AND, XXX, XXX, XXX, AND, ROL, XXX, SEC, AND, XXX, XXX, NOP, AND, ROL, XXX,
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RTI, EOR, XXX, XXX, XXX, EOR, LSR, XXX, PHA, EOR, LSR, XXX, JMP, EOR, LSR, XXX,
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BVC, EOR, XXX, XXX, XXX, EOR, LSR, XXX, CLI, EOR, XXX, XXX, XXX, EOR, LSR, XXX,
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RTS, ADC, XXX, XXX, XXX, ADC, ROR, XXX, PLA, ADC, ROR, XXX, JMP, ADC, ROR, XXX,
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BVS, ADC, XXX, XXX, XXX, ADC, ROR, XXX, SEI, ADC, XXX, XXX, XXX, ADC, ROR, XXX,
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- XXX, STA, XXX, XXX, STY, STA, STX, XXX, DEY, XXX, TXA, XXX, STY, STA, STX, XXX ,
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+ XXX, STA, XXX, XXX, STY, STA, STX, XXX, DEY, XXX, TXA, XXX, STY, STA, STX, SAX ,
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BCC, STA, XXX, XXX, STY, STA, STX, XXX, TYA, STA, TXS, XXX, XXX, STA, XXX, XXX,
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LDY, LDA, LDX, XXX, LDY, LDA, LDX, LAX, TAY, LDA, TAX, XXX, LDY, LDA, LDX, LAX,
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BCS, LDA, XXX, LAX, LDY, LDA, LDX, XXX, CLV, LDA, TSX, XXX, LDY, LDA, LDX, XXX,
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CPY, CMP, XXX, XXX, CPY, CMP, DEC, XXX, INY, CMP, DEX, AXS, CPY, CMP, DEC, XXX,
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BNE, CMP, XXX, XXX, XXX, CMP, DEC, XXX, CLD, CMP, XXX, XXX, XXX, CMP, DEC, XXX,
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CPX, SBC, XXX, XXX, CPX, SBC, INC, XXX, INX, SBC, NOP, XXX, CPX, SBC, INC, XXX,
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- BEQ, SBC, XXX, XXX, XXX, SBC, INC, XXX, SED, SBC, XXX, XXX, XXX, SBC, INC, XXX
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+ BEQ, SBC, XXX, XXX, XXX, SBC, INC, XXX, SED, SBC, XXX, XXX, XXX, SBC, INC, XXX,
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};
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const int MODE_TABLE[256 ] = {
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- IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, XXX ,
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- REL, INDY, INDY, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, XXX ,
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- ABS, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, ABSY, ABSX, ABSX, ABSX, XXX ,
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- IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, XXX ,
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- IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, IND, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, XXX ,
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- IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, ZPX, ZPX, ZPY, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, XXX ,
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+ IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS ,
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+ REL, INDY, INDY, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, ABSX ,
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+ ABS, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, ABSY, ABSX, ABSX, ABSX, ABSX ,
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+ IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, ABSX ,
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+ IMP, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, IND, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, XXX, ZPX, ZPX, XXX, IMP, ABSY, XXX, XXX, XXX, ABSX, ABSX, ABSX ,
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+ IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, ZPX, ZPX, ZPY, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, ABSY ,
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IMM, INDX, IMM, XXX, ZP, ZP, ZP, ZP, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS,
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- REL, INDY, XXX, INDY, ZPX, ZPX, ZPY, XXX, IMP, ABSY, ACC, XXX, ABSX, ABSX, ABSY, XXX ,
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- IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, IMM, ABS, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, ZPX, ZPX, ZPX, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, XXX ,
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- IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, XXX ,
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- REL, INDY, XXX, XXX, ZPX, ZPX, ZPX, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, XXX
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+ REL, INDY, XXX, INDY, ZPX, ZPX, ZPY, XXX, IMP, ABSY, ACC, XXX, ABSX, ABSX, ABSY, ABSY ,
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+ IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, IMM, ABS, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, ZPX, ZPX, ZPX, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, ABSX ,
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+ IMM, INDX, XXX, XXX, ZP, ZP, ZP, XXX, IMP, IMM, ACC, XXX, ABS, ABS, ABS, ABS ,
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+ REL, INDY, XXX, XXX, ZPX, ZPX, ZPX, XXX, IMP, ABSY, ACC, XXX, XXX, ABSX, ABSX, ABSX,
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};
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@@ -497,6 +497,9 @@ void CPU::parse(uint8_t opc) {
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setflags (FLAG_Z, !a);
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setflags (FLAG_N, a & 0x80 );
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break ;
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+ case SAX:
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+ putaddr (addr, a & x);
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+ break ;
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default :
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printf (" cpu: unknown opcode: %02x\n " , opc);
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